So the big news today is how the guys in China finally did another Top500 submission, at #1. To be clear - China has had a ~Top10 HPC system for the past few years - the upgraded TaihuLight - but has refrained from making a submission for fear of reprisals in the form of sanctions. This is probably a good idea - nation-scale systems are unashamedly used for weapons design and flaunting this capability in front of the world when you are not using fully domestic technology will generally lead to a bad ending.
The new submission - LineShine - achieves 2.2EFLOPS on HPL using 45360 Huawei LX2 CPUs connected using a proprietary fat-tree network. The interesting thing here is the LX2 CPU, which is the latest in a series of Chinese HPC processors built with a explicitly-memory-managed, DSP-like architecture. We briefly dive into the architecture below, as well as some historical comparisons.
All HPC devices have a shared memory-global memory architecture, where shared memory is a fast local SRAM accessible by a subset of the processing units and global memory is DRAM which is accessible by all processing units. Where they differ is how this hierarchy is managed:
- CPUs use the shared memory as cache, hiding it entirely from the programmer
- GPUs use the shared memory as cache, but additionally allows explicit shared memory loads
- DSPs only allow computation on shared memory, relying on explicit loads to transfer data from global memory
Additionally, CPU/DSPs and GPUs differ in how they expose parallelism to programmers:
- CPU/DSPs explicitly reveal cores and SIMD lanes: there are N cores, each of which an execute m operations per cycle
- GPUs abstract cores x SIMD lanes as threads: to the programmer, there are N threads, each of which work on one element at a time. Internally, GPUs are a complex share-resource SIMD multicore processor - GPU "cores" are not fully independent of each other, but are more so than the SIMD lanes in a CPU
The LineShine/Huawei LX2 is a 304-core ARM DSP which is physically two 152-core processors and electrically 8 38-core core groups. Each core group has access to 4 GB of HBM and each 152-core processor has access to 128 GB of DDR5. While it appears that cores do have access to memory directly via load/store instructions (as an ARMv9-compliant device, it would be impossible not to), the primary way of memory access is through the DMA engines, a block which lives in the uncore and asynchronously moves data between memory levels.
The most famous DMA-driven processor was the Cell Broadband Engine, a 1 8 core DSP where the 8 cores could only access data via DMA transfers. Its spiritual successor is the Sunway SW26010P, a 384-core processor built as 6 64-core complexes, each in the same style as Cell. LX2 is a divergence from the pure DMA architecture - there is no management core - but the idea remains the same: explicit programmer management of data transfer leads to high performance in the hands of a skilled programmer.
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