🧵 Today we're sharing a deep dive into Huawei's ‘Tao (τ) Law’, written by 乱序摸鱼, a Huawei HiSilicon chip architect.
As traditional scaling becomes increasingly difficult, the semiconductor industry is searching for the next growth curve.
Huawei's proposal is both ambitious and practical:
Use 3D integration not just as a packaging technology, but as a new design paradigm for future mobile SoCs.
This isn't simply about stacking more silicon.
It's about turning 3D space into a first-class design dimension for architecture, packaging, thermals, power delivery, and even OS scheduling.
The article explores a bigger question: What comes after conventional transistor scaling?
Let's dive in 👇
1️⃣ Why Mobile Chips Need A New Direction
Mobile devices want everything at once:
• more AI
• bigger batteries
• better cameras
• higher performance
• lower power
But motherboard space isn't growing.
Meanwhile, traditional 2D scaling is becoming increasingly expensive, both economically and physically.
The next frontier may not be smaller transistors alone.
It may be learning how to build upward.
🏗️ In other words, future gains may come from architectural density, not just transistor density.
2️⃣ Huawei Didn't Invent 3D ICs
The industry has been exploring 3D integration for years:
• AMD's 3D V-Cache
• Intel Foveros
• TSMC SoIC
• Apple's UltraFusion
The real question isn't: "Can chips be stacked?"
It's - "Can core logic itself be folded across multiple layers?"
That's a much harder problem.
Most existing solutions focus on:
• cache stacking
• chiplet integration
• package-level interconnects
Huawei's discussion goes further:
⚡ Can CPU, GPU, NPU and cache structures themselves be partitioned across multiple silicon layers?
3️⃣ Why Wafer-to-Wafer Matters
Huawei's proposed direction isn't traditional chiplets.
It's wafer-to-wafer face-to-face bonding.
Why?
Because logic folding requires extremely dense vertical interconnects.
The goal isn't modularity, but making two logic layers behave like one piece of silicon.
🔬 Compared with conventional packaging approaches, wafer-level hybrid bonding can dramatically reduce:
• interconnect length
• latency
• energy per bit transferred
Those benefits become critical once logic starts spanning multiple dies.
4️⃣ Why 1.5μm Pitch Matters
Pitch determines how many vertical connections can fit into a given area.
Smaller pitch means:
✅ higher bandwidth
✅ shorter signal paths
✅ lower communication energy
❌ lower yield
❌ harder manufacturing
❌ tighter process control requirements
The article argues that 1.5μm hybrid-bonding pitch is aggressive enough to enable meaningful logic folding, while remaining manufacturable at scale.
📈 At this density, vertical connectivity begins approaching the scale needed for true logic-level integration rather than simple die stacking.
5️⃣ The Real Battle: Partitioning
This may be the most important challenge in the entire stack.
Where should CPU blocks go? What about GPU, NPU, cache, clocks and power networks?
A bad partition creates:
• thermal hotspots
• routing congestion
• timing failures
• excessive cross-die traffic
A good partition unlocks most of the benefits of 3D integration.
Before physical design begins, the architecture battle has already started.
🧠 This is fundamentally a system-level optimization problem balancing:
performance × power × thermal × manufacturability
6️⃣ TSVs Turn Everything Into DTCO
TSVs aren't just vertical wires. They introduce:
• mechanical stress
• routing blockage
• thermal impact
• yield penalties
Every decision becomes a DTCO problem: architecture × process × packaging × layout
In 3D chips, everything is connected.
⚙️ A TSV placement decision can affect:
• timing closure
• thermal distribution
• power delivery
• manufacturing yield
This is why 3D IC design pushes DTCO (Design-Technology Co-Optimization) to a completely different level.
🔗 Full thinking:
zhihu.com/question/204219473…
#AI #Semiconductor #Huawei #Kirin #ChipDesign #EDA #AIInfra #Hardware #Computing
